The present invention relates generally to telecommunication systems and specifically to a system for minimizing the number of processor cycles required for implementing compression and decompression algorithms, while maintaining flexibility.
In a telecommunication system, a voice signal is sampled by an analog to digital converter. Data output from the converter is a linear representation of the voice signal. The linear data is typically encoded using a compression algorithm, such as μ-Law or A-Law. μ-Law is a Texas Instruments (TI) standard algorithm describing nonlinear compression performed in an analog-to-digital conversion of pulse code modulated (PCM) systems used in the U.S.A., Canada, and Japan. A-Law is a Conference for European Postal and Telecommunications administrations (CEPT) standard algorithm describing non-linear compression performed in an analog-to-digital conversion of PCM systems used in Europe and most other countries. The encoded data is transmitted across a network. At a receiving end of the network, the data is decoded. The decoded signal is passed through a digital-to-analog converter to generate an analog voice signal.
Typically, the μ-law and A-law encoder and decoder algorithms are implemented in either hardware or software. A first solution is to implement the algorithms as a hardware block in a datapath. Thus, all data going through the datapath is either encoded or decoded. While such an approach is efficient, it is inflexible and, thus, inappropriate for some systems.
An alternate solution is to implement the algorithms using software, or on a processor, to allow increased flexibility as compared to the hardware solution. However, the algorithms can consume a large number of processor cycles, especially if a processor is servicing many different channels. While such as approach is flexible, it is time consuming and, thus, inappropriate for some systems.
Yet an alternate solution is to implement the algorithms using standalone hardware blocks, accessible to the processor through its memory or input/output interface. However, these interfaces tend to be slower than internal processor operations. Thus, while such a solution can be an improvement over the previous solutions, it can still consume a significant number of processor cycles.
Therefore, there is a need for a system that implements the compression and decompression algorithms and provides flexibility, while reducing the required number of processor cycles. It is an object of the present invention to obviate or mitigate at least some of the above-mentioned disadvantages.